- Raj Parihar, Microsoft (email@example.com)
- Michael Goldfarb, Qualcomm (firstname.lastname@example.org)
Publicity and Outreach
- Debu Pal, Cadence
- Mahdi Bojnordi, University of Utah
- Krishna Nagar, Intel
- Tao Sheng, Amazon (email@example.com)
- Sikandar Mashayak, Wave Computing (firstname.lastname@example.org)
- Satyam Srivastava, Intel (email@example.com)
- Sushant Kondguli, Samsung (firstname.lastname@example.org)
- Marwane Hariat, Wave Computing
- Khalid Tahboub, Qualcomm
- Smriti Ojha, AMD
- Shuai Zhang, Qualcomm
- Ali Shafiee, University of Utah
- Partha Maji, Arm ML Research
- Karl Taht, University of Utah
- Urmish Thakker, Arm
- Vinayak Gokhale, Google
- Claudionor Coelho, Google
- Aliasger Zaidy, FWDNXT Inc.
- Zheng Wang, Amazon
- Pradeep Ramani, NVIDIA
- Amrit Panda, Microsoft
- Tijmen Blankevoort, Qualcomm
- Sikandar Mashayak, Wave Computing Inc.
- Jain Karishma, Intel
- He Xiao, Cadence
- Wei Wang, Amazon
- Tushar Krishna, Georgia Institute of Technology
- Nader Sehatbakhsh, Georgia Institute of Technology
- Balajee Vamanan, University of Illinois at Chicago
- Xia Lu, Amazon
- Rahmani Mariam, Intel
- Keshari Rishabh, Intel
- Kushal Datta, Intel
- Andre Xian Ming Chang, Purdue University
- Sylvain Flamant, Wave computing
- Rosario Cammarota, Intel
- Chen Ding, University of Rochester
- Andy Glew, NVIDIA
- Sreepathi Pai, University of Rochester
- Raj Jain, Washington University
- Smruti Sarangi, IIT Delhi
- Shaoshan Liu, PerceptIn
- Ali Shafiee, Samsung
- Danian Gong, Cadence
About the Organizers
Dr. Raj Parihar is currently a Senior Performance Architect at Microsoft in Silicon Engineering Group. His research interests are computer architecture, neural network accelerator architectures and memory subsystem design. In the past, while working at Cadence Tensilica, Raj was involved in architectural exploration, performance modeling and analysis of neural network AI processor DNA 100. He also contributed to the microarchitectural enhancements (next generation branch predictors and cache prefetchers) of P-series Warrior cores at MIPS/ImgTech. His work on Cache rationing won the best paper award at ISMM’16. Dr. Parihar received his Doctorate and Masters from University of Rochester, NY and his Bachelors from Birla Institute of Technology & Science, Pilani, India.
Michael Goldfarb is a Senior Staff Engineer at Qualcomm working on HW/SW architecture for machine learning. Previously he was working at NVIDIA on various projects in the Compute Architecture group for high performance training, specifically compilers, kernels and architecture for deep learning. Prior to that, he was at Qualcomm Research where he worked on optimizing AI/ML applications for Snapdragon powered devices and developed new accelerator architectures for low power on device inference. His research interests are in machine learning, compilers, parallel programming and accelerator architecture. Michael received his Masters and Bachelors degrees from Purdue University (West Lafayette, IN).
Dr. Satyam Srivastava is a Senior Software Engineer in the Software and Services Group at Intel corporation. He works on machine learning enabling and applications on devices and in the cloud. In his prior role he worked on Intel graphics software to accelerate media processing. His interests include visual computing, machine learning, and compute accelerators. Dr. Srivastava obtained his Doctorate degree from Purdue university (West Lafayette, IN) and Bachelor’s degree from Birla Institute of Technology and Science, Pilani (India).
University of Utah
Dr. Mahdi N. Bojnordi received the Ph.D. degree in electrical and computer engineering from the University of Rochester, Rochester, NY, USA, in 2016. He is currently an Assistant Professor at the School of Computing, University of Utah, Salt Lake City, UT, USA, where he leads the Energy-Efficient Computer Architecture Laboratory. His current research interests include energy-efficient architectures, low-power memory systems, and the application of emerging memory technologies to computer systems. Dr. Bojnordi received the two IEEE Micro Top Picks Awards, the HPCA 2016 Distinguished Paper Award, and the Samsung Best Paper Award for his research.
Dr. Tao Sheng is a Senior Deep Learning Engineer at Amazon. He has been working on multiple cutting-edge projects in the research areas of computer vision, machine learning in more than 10 years. Prior to Amazon, he worked with Qualcomm and Intel. He has strong interests in deep learning for mobile vision, edge AI, etc. He has published ten US and International patents and eight papers. Most recently, he led the team to win the First Prize of IEEE International Low-Power Image Recognition Challenge (LPIRC-I) at CVPR 2018 and win top two Prizes at LPIRC-II 2018 among a wide variety of global competitors.
Dr. Krishna Nagar is a SoC Design Engineer at Intel Corporation. He is the lead architect for Qsys Interconnect and Avalon bus protocols. His research interests include reconfigurable computing, NoC and floating point computer arithmetic. Dr. Nagar received his Doctorate and Master’s degree in Computer Engineering from University of South Carolina, SC and his Bachelors from Rajiv Gandhi Technical University, India.
Dr. Debajyoti (Debu) Pal currently holds the position of Chief Scientist, Machine Learning at Cadence IP Group. Prior to Cadence, he was Vice President, Machine Learning at Wave Computing Inc. Before joining Wave Computing, Debu served as Vice President of Technology at Qualcomm Inc. Prior to Qualcomm, he was Senior Vice President and Chief Technology Officer of Ikanos Communications. Debu has served as Chief Technology Officer and Executive in Residence at Tallwood Venture Capital. Prior to Tallwood, he was Vice President of Engineering at Virata Corporation and GlobespanVirata, Inc. He cofounded Excess Bandwidth Corporation (with Prof. Thomas Kailath of Stanford University) and was Chief Technology Officer and Vice President, Engineering until Virata acquired it. He holds eight granted U.S. patents, has published more than 20 technical papers. Debu was a Consulting Professor of Electrical Engineering at Stanford University between 1997 and 2009. He became a Fellow of the IEEE in 2002 for his Contributions to Digital Communications.
Dr. Sushant Kondguli is currently a GPU Architect at the Advanced Computing Lab in Samsung where he is involved in architectural exploration, performance modeling and analysis of GPUs. His research interests are in Computer Architecture, Computer Graphics and Machine Learning. He received his PhD degree in Electrical and Computer Engineering from the University of Rochester, Rochester, NY and Bachelors in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India
Sikandar Y. Mashayak is a Staff Research and Development Engineer in AI Core Technologies team at Wave Computing Inc, Campbell, CA. At Wave, he is developing fast, efficient, and accurate neural network models and co-designing mixed-precision neural network training and inference algorithms for AI accelerator hardware. His research interests are in machine learning, NN model compression (pruning and quantization), co-design AI algorithms, numerical modeling, optimization, and heterogeneous parallel computing. He received his Ph.D. from the University of Illinois at Urbana-Champaign, the M.S. degree from Purdue University, W. Lafayette, IN, and the B.E. (Hons.) degree from Birla Institute of Technology and Science, Pilani, India.